Method for the double-side polishing of a semiconductor wafer

ABSTRACT

A method of simultaneous double-side polishing of a front side and a rear side of at least one wafer composed of semiconductor material includes disposing each wafer in a respective suitably dimensioned cutout in a carrier plate. The at least one wafer is polished on the front side and on the rear side between an upper polishing plate covered with a first polishing pad and a lower polishing plate covered with a second polishing pad while supplying a polishing agent. A respective surface of each of the first and second polishing pads is interrupted by at least one respective channel-shaped depression running spirally from a center to an edge of the respective pad.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority to German Patent Application No. DE 102011 082 777.3, filed Sep. 15, 2011, which is hereby incorporated byreference herein in its entirety.

FIELD

The invention relates to a method for the double-side polishing of asemiconductor wafer.

BACKGROUND

At the present time, predominantly polished or epitaxially coatedsilicon wafers having a diameter of 300 mm are used for the mostdemanding applications in the electronics industry. Silicon wafershaving a substrate diameter of 450 mm are in development.

However, the enlargement of the substrate diameter is accompanied bymajor, in some instances also totally new, hitherto unknown technicalproblems.

Many processing steps, whether they are of purely mechanical (sawing,grinding, lapping), chemical (etching, cleaning) or chemical-mechanicalnature (polishing), and also the thermal processes (epitaxial coating,annealing), require thorough revision, in part also with regard to themachines used therefor and the working materials.

Semiconductor wafers, after being sliced from a single crystal (ingot)composed of semiconductor material, are processed further in amultiplicity of process steps. After the grinding, cleaning and etchingsteps, in accordance with the prior art, the surface of thesemiconductor wafers is smoothed by one or a plurality of polishingsteps.

Obtaining a sufficiently good edge geometry and the surface flatness(nanotopology) are particularly critical in the manufacture ofsemiconductor wafers.

The nanotopology is usually expressed as height fluctuation PV (=“peakto valley”), relative to square measurement windows having an area of 2mm×2 mm.

The final nanotopology of a semiconductor wafer is generally produced bymeans of a polishing process.

In the case of single-side polishing (SSP), semiconductor wafers areheld during processing on the rear side on a support plate by means ofcement, a vacuum or by means of adhesion and are subjected to polishingon the other side.

In the case of double-side polishing (DSP), semiconductor wafers areinserted loosely into a thin carrier plate and are polished on the frontand rear sides simultaneously in a “freely floating” manner between anupper and a lower polishing plate each covered with a polishing pad.This polishing method is effected with the supply of a polishing agentslurry, usually based on a silica sol.

The prior art likewise discloses polishing using fixedly bondedabrasives (“Fixed Abrasive Polishing”, FAP), wherein the semiconductorwafer is polished on a polishing pad which, in contrast to otherpolishing pads, contains an abrasive substance bonded in the polishingpad (“Fixed Abrasive” or FA pad). The German Patent Application DE 102007 035 266 A1 describes a method for polishing a substrate composed ofsilicon material, using FA pads.

After DSP or FAP, the front sides of the semiconductor wafers aregenerally polished in a haze-free manner. As is usually effected using asofter polishing pad with the aid of an alkaline polishing sol. In theliterature, this step is often designated as chemical mechanicalpolishing (CMP). CMP methods are described, for example, in US2002-0077039 and in US 2008-0305722.

100141 By comparison with single-side polishing (SSP), simultaneousdouble-side polishing (DSP) of semiconductor wafers is not only moreeconomic, but higher flatness with regard to the surfaces of thesemiconductor wafers is obtained as well.

Double-side polishing is described, for example, in U.S. Pat. No.3,691,694. A suitable double-side polishing machine is described in DE100 07 390 A1. In accordance with one embodiment of double-sidepolishing as described in EP 0 208 315 B1, semiconductor wafers incarrier plates composed of metal or plastic, which have suitablydimensioned cutouts, are moved between two rotating polishing platescovered with a polishing pad in the presence of a polishing agent(polishing sol) on a path predetermined by the machine and processparameters and are thereby polished (in the literature, carrier platesare designated as “templates”).

The double-side polishing step is usually carried out using a polishingpad composed of homogeneous, porous polymer foam having a hardness of 60to 90 (Shore A), as described for example in DE 100 04 571 C1, where itis also disclosed that the polishing pad adhering to the upper polishingplate is pervaded by a network of channels and the polishing padadhering to the lower polishing plate has a smooth surface without sucha texture. This measure is intended firstly to ensure a homogeneousdistribution of the polishing agent used during polishing and secondlyto prevent the semiconductor wafer from adhering to the upper polishingpad when the upper polishing plate is raised after polishing hasfinished.

The upper polishing pad comprises a regular chequered arrangement ofchannels having a segment size of 5 mm×5 mm to 50 mm×50 mm and a channelwidth and depth of 0.5 to 2 mm. This arrangement is used to effectpolishing at a polishing pressure preferably of 0.1 to 0.3 bar. Thesilicon removal rate is preferably between 0.1 and 1.5 μm/min andparticularly preferably between 0.4 and 0.9 μm/min.

However, a procedure in accordance with DE 100 04 578 C1 results in anasymmetrical polishing removal at the outer edge of the semiconductorwafer at the opposite sides (rear side and front side).

A further cause of locally different polishing removals in the case ofdouble-side polishing in accordance with the prior art is the fact thatabraded material (semiconductor material, for example silicon or siliconoxide), removed from the surfaces of the semiconductor wafers in thepolishing process covers (deposits on) the polishing pad surfaces to inpart different extents. In particular, the regions of the polishing padsurface which come into contact with the surfaces of the semiconductorwafers during the polishing process the most often statistically in adefined time period are covered with abraded material. A ring-shapedarea with abraded material often forms on the polishing pad surface.

The formation of regions covered with abraded material on the polishingpad surface is additionally fostered by a non-uniform polishing agentdistribution in the working gap between polishing pad and carrier plate.

The areas of the polishing pad which are covered with abraded materialconstitute regions in which the pad is altered in terms of its textureand in terms of its composition near the surface. These regionstherefore have different properties with regard to the polishing resultin comparison with the regions which are affected to a lesser extent ornot at all by covering with abraded material.

As polishing pad covering increases, it becomes more and more difficultto control the polishing machines in such a way that flat wafers havinggood geometry values (GBIR, wafer shape, edge roll-off) are produced.Furthermore, it is necessary to reckon with an increase in the microroughness (haze values) of the wafers. The risk of polishing scratchesand increased LLS values on the polished wafer surfaces likewiseincreases in a similar manner,

Regular polishing pad conditioning that becomes necessary as a resultreduces the lifetime of the polishing pads (wear) and additionallyadversely impairs on account of the mechanical action on the polishingpad and the associated change in the polishing pad (thickness, padstructure, . . . )—the wafer geometry and form.

A further cause of the non-uniform polishing removal is, inter alia, apolishing agent distribution effected non-uniformly on the polishing padand, as a consequence thereof, a non-uniform wetting of the surfaces tobe polished with polishing agent, or application of polishing agent tosaid surfaces.

In accordance with the prior art, the polishing agent distribution iseffected by gravitational force and centrifugal force. The polishingagent is introduced from above into the working gap between polishingpad and carrier plate and flows on account of the gravitational forceinter alia through the cutouts for the semiconductor wafers in thecarrier plate also onto the lower polishing pad. In this case, thepolishing agent distribution is fostered by the rotational movement ofthe carrier plates and of the polishing plates covered with thepolishing pads.

The uniform polishing agent distribution is impeded by the carrierplate., in particular with regard to the polishing pad regions lyingbelow the carrier plate in order to improve the polishing agentdistribution, US 2006-178089 A describes a carrier plate having amultiplicity of round openings through which the polishing agent reachesthe lower polishing pad.

The teaching of EP 1 676 672 A1 includes improving the supply ofpolishing agent to the lower polishing plate by at least 15% of the areaof the carrier plate being occupied by holes that provide for thepolishing agent a passage to the lower polishing plate.

However, these additional “polishing agent cutout” in the circularcarrier plates reduce the area moment of inertia thereof and, as aconsequence thereof, also the resistance thereof to torsion. That isdisadvantageous since the risk of carrier plate warping is therebyincreased. The warping of the carrier plate can lead to pad damage,reduced pad lifetime, particle generation, polishing scratches throughto wafer fracture and damage to the installation.

On account of the further increasing surface area in semiconductorwafers of future generations, for example having a diameter of 450 mm,the uniform polishing agent distribution (application of polishingagent) can be realized only to a limited extent during the polishingprocess in accordance with the prior art.

SUMMARY

In an embodiment, the present invention provides a method ofsimultaneous double-side polishing of at least one wafer having a frontside and a rear side and composed of semiconductor material includingdisposing each wafer in a respective suitably dimensioned cutout in acarrier plate. The at least one wafer is polished on the front side andon the rear side between an upper polishing plate covered with a firstpolishing pad and a lower polishing plate covered with a secondpolishing pad while supplying a polishing agent. A respective surface ofeach of the first and second polishing pads is interrupted by at leastone respective channel-shaped depression running spirally from a centerto an edge of the respective pad.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the present invention are described in moredetail below with reference to the drawings, in which:

FIGS. 1 a-1 d show spiral forms used in embodiments of a methodaccording to the invention: and

FIG. 2 shows an embodiment of a carrier plate including polishing agentpassages.

DETAILED DESCRIPTION

In an embodiment, the present invention provides a method that promotesthe uniform application of polishing agent to the polishing pad surfacesduring the simultaneous double-side polishing of semiconductor wafers,without impairing the stability of the carrier plate.

In an embodiment, the present invention provides a method for thesimultaneous double-side polishing of at least one wafer composed ofsemiconductor material which is situated in a suitably dimensionedcutout in a carrier plate and which has a front side and a rear side,and the double-side polishing is effected between an upper polishingplate covered with a first polishing pad and a lower polishing platecovered with a second polishing pad, with a polishing agent beingsupplied, wherein the surfaces of the first (upper) and of the second(lower) polishing pad are in each case interrupted by at least onechannel-shaped depression running spirally from the center to the edge.

FIG. 1 shows spiral forms used in embodiments of the method according tothe invention: (a) logarithmic spiral, (b) Archimedes' spiral, (c)Fermat's spiral, (d) triple spiral,

FIG. 2 shows a preferred embodiment of the carrier plate (1) modifiedaccording to the invention with the segmented polishing agent passages(2) interrupted by the three webs (4), and the suitably dimensionedcutouts (3) for the wafers (5) composed of semiconductor material,wherein the cutouts (3) for the wafers (5) composed of semiconductormaterial are surrounded by the segmented polishing agent passages (2) ata distance A. In this preferred embodiment, the webs (4) are arrangedsuch that the respective centers of the three webs (4) are at an angleof 120° with respect to one another.

The process includes not just a partial aspect restricted to a specifictechnical component or an individual process-technological aspect (e.g.of individual process parameters), but encompasses associated processfeatures. These process features are subdivided into

1) Polishing pads having a specific surface structure,

2) Reconfiguration of the carrier plates for wafer accommodation and

3) Polishing agent supply effected on both sides.

In an embodiment, the process for the simultaneous double-side polishing(DSP) of a wafer composed of semiconductor material uses a polishingagent made of a silica sol, a slurry comprising colloidally distributedparticles having a size of 20 to 50 nm.

The polishing agent distribution during DSP is influenced, inter alia,by the properties of the polishing pad surface (working surface) whichcomes into contact in a material-removing manner with the front and/orrear side of the semiconductor wafer during the polishing process. Boththe absorbency for the polishing agent and the structure (channels,depressions, grooves) influence the polishing agent distribution duringDSP, as is described for example in DE 100 04 578 C1.

Circular polishing pads composed of homogeneous, porous polymer foam haa hardness of 60 to 90 (Shore A) can be used for the method according tothe invention.

In a first exemplary embodiment of the method according to the inventionfor the simultaneous double-side polishing of wafers composed ofsemiconductor material, the upper and the lower polishing plate arecovered with circular polishing pads, the working surface of which isprovided with at least one channel (depression, groove) runningspirally.

A spiral channel is a depression that runs circularly around a startpoint and depending on the running direction (orientation), leads awayfrom said point or approaches said point. The distance between twospiral channels (distance W between the turns) can be constant(Archimedes' spiral (FIG. 1 b)) or—as viewed from the start point—canbecome continuously greater (logarithmic spiral (FIG. 1 a)).

A special form of spiral is the triple spiral, which consists of threeArchimedes' spirals arranged circularly around a midpoint and whoselines, after a finite number of turns, form a circular form enclosingthe three spirals (FIG. 1 d).

For the method according to embodiments of the invention for thesimultaneous double-side polishing of wafers composed of semiconductormaterial, use is preferably made of polishing pads having at least onechannel running spirally from the inner portion (middle or center of thepolishing pad) toward the outer portion (edge of the polishing pad) onthe working surface, characterized in that the distance W between theturns of the at least one spiral channel becomes continuously greaterfrom the inner portion toward the outer portion (logarithmic spiral,FIG. 1 a).

For the method according to embodiments of the invention for thesimultaneous double-side polishing of wafers composed of semiconductormaterial, preference is likewise given to using polishing pads havingchannels running spirally from the inner portion toward the outerportion on the working surface, characterized in that the distance Wbetween the turns of the channels becomes continuously smaller from theinner portion toward the outer portion (Fermat's spiral, FIG. 1 c).

Particularly preferably, for the method according to the invention forthe simultaneous double-side polishing of wafers composed ofsemiconductor material, use is made of polishing pads having channelsrunning spirally from the inner portion toward the outer portion on theworking surface, characterized in that the distance W between the turnsof the channels is constant (Archimedes' spiral, FIG. 1 b).

The distance W between turns between two spiral channels on thepolishing pad surface is chosen such that—independently of the diameterof the circular polishing pad—the spiral has at least 3 turns.

Preferably, a spirally arranged channel running from the center of thepolishing pad (start point) spirally to the edge region of the polishingpad is situated in the surface of the polishing pad. In this case, theend point of this spiral depression can reach as far as the edge of thepolishing pad,

In a likewise preferred embodiment of the method according to theinvention, two or more spirally arranged channels running from thecenter of the polishing pad (start point) to the edge thereof aresituated in the surface of the polishing pad.

In this embodiment,particular preference is given to polishing padswhose working surface has in an inner circular region around themidpoint of the circular polishing pad having a radius R three channelsrunning spirally from the center of the polishing pad toward the edge,wherein, in a ring-shaped outer region (edge region) of the polishingpad surface, having a thickness D, the three spiral channels merge intoa circular course (triple spiral, FIG. 1 d).

The radius R of the inner circular region of the polishing pad surfaceis preferably greater than or equal to two thirds of the radius of thecircular polishing pad. In this case, the thickness D of the outerring-shaped region is preferably less than or equal to one third of theradius of the circular polishing pad and results from the difference inthe outer radius of the ring-shaped edge region minus the inner radiusof the ring-shaped edge region.

The spiral channels have a preferred depth of 0.5-1.5 mm and a preferredwidth of 1-5 mm. Particularly preferably, the spiral channels have adepth of 0.7-1.0 mm and a width of 1.5-3 mm.

Preference is likewise given to an enlargement of the width of thespiral channels from the inner portion toward the outer portion, saidenlargement running uniformly over the length of the channels from thestart point to the end, wherein the width is preferably 2 mm at thebeginning of the spiral channel (in the center of the circular polishingpad) and is preferably 4 mm at the end of the spiral channel (in theedge region or at the edge of the circular polishing pad).

By virtue of the greater width of the spiral channel on the workingsurface of the polishing pad in comparison with the width of the spiralchannel in the pad center, the distribution of the polishing agent isadditionally optimized.

According to an embodiment of the invention, the polishing agentdistribution in the working gap can also be effected by an enlargementof the depth from the inner portion toward the outer portion, saidenlargement running uniformly over the length of the spiral channel fromthe start point to the end thereof, wherein the depth is preferably 0.5mm at the beginning of the spiral channel (in the center of the circularpolishing pad) and is preferably 1 mm at the end of the spiral channel(in the edge region or at the edge of the circular polishing pad).

The inner form of the spiral channel preferably has a half-round form(U-profile). A rectangular inner form of the spiral channel is likewisepreferred.

The edge that arises between the polishing pad surface and thedepression formed by the spiral channel is preferably rounded.

Preferably, the channels arranged spirally into the surfaces of thepolishing pads are oriented in the same sense. The use of spiralchannels oriented in the same sense in the polishing pad surface—andthus the use of fundamentally identical polishing pads—is possible sincethe polishing plates face one another with their end sides—and thus alsothe active polishing pad surfaces—and upper and lower polishing platesrotate oppositely (diametrically oppositely).

By virtue of the centrifugal force that arises upon the rotation of theworking disks respectively covered with a polishing pad according to theinvention, the polishing agent is transported in the spiral channelsfrom the inner portion toward the outer portion and is distributeduniformly in the working gap formed by the distance between the twopolishing pad surfaces.

For further optimization of the polishing agent distribution during theDSP, in accordance with the method according to the invention, inaddition to the use of the working surfaces of the polishing pads thatare provided with spiral channels according to the invention, thecarrier plates serving for accommodating and guiding the semiconductorwafers can also be configured.

A carrier plate used during DSP consists, in accordance with the priorart, of a round disk having one or a plurality of suitably dimensionedcutouts (3) into each of which a wafer (5) composed of semiconductormaterial is inserted. In addition, carrier plates can have “polishingagent cutouts” through which the polishing agent introduced into theworking gap from above passes to the lower polishing plate.

Independently of the respective embodiments of the method according tothe invention,in the method according to the invention each wafercomposed of semiconductor material is preferably placed into a suitablydimensioned round cutout in the carrier plate such that the front sideof the wafer composed of semiconductor material is polished at the upperpolishing pad.

In the second exemplary embodiment of the method according to theinvention for the simultaneously double-side polishing of waferscomposed of semiconductor material, modified carrier plates are usedinstead of the carrier plates in accordance with the prior art.

The carrier plate (1) modified according to the invention has at leastone suitably dimensioned cutout (3) for accommodating a wafer (5)composed of semiconductor material, characterized in that the at leastone suitably dimensioned cutout (3) is surrounded by at least onefurther cutout (2), acting as a polishing agent passage, at a distanceA.

Preferably, the carrier plate (1) modified according to the inventionhas at least one suitably dimensioned circular cutout (3) foraccommodating a wafer (5) composed of semiconductor material,characterized in that at least one circular cutout (3) is surrounded bythree segmented cutouts (2) which have an identical size (relative tothe area) and are separated by webs (4), with a distance among oneanother of in each case at most 110°, in a ring-shaped manner at adistance A from the circular cutout (3) (FIG. 2).

The preferred thickness of the segmented cutout (2), which results fromthe difference in the outer edge minus the inner edge, is 1-10 mm.Particularly preferably, the thickness of the segmented cutout (2) is3-7 mm. The preferred distance A between the outer edge of the circularcutout (3) and the inner edge of the segmented cutouts (2) is constantand is 5 to 10 mm.

The segmented “polishing agent cutouts” (2) in the carrier plate (1)modified according to the invention do not influence the stability ofthe carrier plate.

In the carrier plate (1) modified according to the invention, arespective semiconductor wafer (5) can be inserted into a suitablydimensioned cutout (3) in the carrier plate (1) and positioned such thatan inherent rotation of the semiconductor wafer (5) within the cutout(3) in the carrier plate (1) is possible during the polishing process.

In a further preferred embodiment of the carrier plate (1) modifiedaccording to the invention, the inherent rotation of the at least onesemiconductor wafer (5) in the suitably dimensioned cutout (3) in thecarrier plate (1) is prevented by the fixing of the semiconductor wafer(5) during the polishing process.

The fixing of the semiconductor wafer (5) in the suitably dimensionedcutout (3) in the carrier plate (1) can be effected, for example, withthe aid of one or a plurality of so-called “notch fingers”.

A “notch finger” is a protuberance for example in the suitablydimensioned cutout (3) in the carrier plate (1) which projects into anotch in the edge of the semiconductor wafer (5) and thus fixes thesemiconductor wafer (5) in the cutout (3) in the carrier plate (1).

In the third exemplary embodiment of the method according to theinvention for the simultaneous double-side polishing of wafers composedof semiconductor material, the polishing agent supply is effectedsimultaneously on the front side and on the rear side of thesemiconductor wafer both through the upper and through the lowerpolishing plate.

For this purpose the polishing agent supply is preferably effected in apressurized manner through openings integrated in the polishing agentoutlets of the two polishing plates such that the outlets terminateflush with the polishing plates.

Particularly preferably, the polishing agent supply is effected in apressurized manner by means of nozzles integrated in the polishing agentoutlets of the two polishing plates such that the nozzle outletsterminate flush with the polishing plates or end within the openings inthe polishing plates.

The two circular polishing pads applied to the upper and lower polishingplates before the polishing process likewise have openings besides thespiral depressions, wherein the number and distribution of the openingson the polishing plate corresponds to the number and distribution of theopenings in the polishing pad and the polishing pad is applied to thepolishing plate in such a way that the polishing agent can pass throughthe openings from above and below into the working gap.

Preferably, the polishing agent outlets for the application of polishingagent are arranged circularly in the polishing plates and pads.Particularly preferably, the polishing agent outlets are arranged in aninner circular and an outer ring-shaped region, wherein the radius R ofthe inner circular region of the polishing plate or polishing pad ispreferably greater than or equal to two thirds of the radius of thecircular polishing plate or polishing pad.

For further optimization of the polishing agent distribution, thequantity of the polishing agent emerging from the nozzles into theworking gap per unit time in an inner circular region of the polishingpad can preferably be higher than the quantity that emerges in the sametime from the nozzles situated in the outer ring-shaped region. As aresult, an “aquaplaning” effect as a result of an excessively highquantity of polishing agent in the working gap can be counteracted in atargeted manner,

The different quantities of polishing agent per unit time can be set,for example, by means of different nozzle cross sections, nozzle typesor by means of nozzles driven individually by pumps.

The nozzles for the polishing agent supply or the openings in thepolishing plate or polishing pad are preferably perpendicular to thesurface of the polishing plate or polishing pad. Particularlypreferably, the nozzles for the polishing agent supply or the openingsin the polishing plate or in the polishing pad have an angle, relativeto the polishing pad surface, of from 45° to less than or equal to both90°, wherein the openings are present in the upper and in the lowerpolishing plate and also in the upper and in the lower polishing pad.

In order to prevent the silica sol particles from crystallizing out(gelation) in the nozzles or lines of the polishing agent supply, thenozzles are rinsed with water after the conclusion of the polishingprocess.

In order also to additionally optimize the polishing result with regardto homogenizing the polishing removal—a plane-parallel wafer initialgeometry is a precondition here, however—the temperature of thepolishing agent supplied ideally corresponds to the surface temperatureof the polishing pads. This is achieved by corresponding temperatureregulation of the polishing plates and of the polishing agent accordancewith the prior art. Preferably, the temperatures of the polishing agentand of the polishing plate lie in the range of 20° C. to 30° C., andespecially preferably in a range of 23° C. to 27° C.

The method according to the invention for the simultaneous double-sidepolishing of wafers composed of semiconductor material can also becombined with an apparatus for polishing agent recycling. For thispurpose, the used polishing agent, which emerges from the working gapvia a lateral outlet, is prefiltered and collected in a container andreplenished in a controlled manner with water, flesh polishing agent andKOH, and pumped back via a filter into the supply container for thepolishing agent. In this case, temperature regulation ensures that thepreferred temperatures of the polishing agent are maintained.

The individual aspects of the method according to the invention interactsuch that at the end a more homogeneous polishing agent distributionbecomes possible directly on site on the polishing pad and,consequently, the material removal on each semiconductor wafer duringthe DSP is made more uniform.

While the invention has been particularly shown and described withreference to preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade therein without departing from the spirit and scope of theinvention.

What is claimed is: 1: A method of simultaneous double-side polishing ofat least one wafer having a front side and a rear side and composed ofsemiconductor material, the method comprising: disposing each wafer in arespective suitably dimensioned cutout in a carrier plate; polishing theat least one wafer on the front side and on the rear side between anupper polishing plate covered with a first polishing pad and a lowerpolishing plate covered with a second polishing pad while supplying apolishing agent, a respective surface of each of the first and secondpolishing pads being interrupted by at least one respectivechannel-shaped depression running spirally from a center to an edge ofthe respective pad. 2: The method recited in claim 1, wherein the atleast one channel-shaped depression running spirally in each polishingpad surface has at least three turns. 3: The method recited in claim 1,wherein a distance W between the turns of the at least onechannel-shaped depression running spirally in each polishing pad surfaceis constant from an inner portion toward an outer portion. 4: The methodrecited in claim 1, wherein a distance W between turns of the at leastone channel-shaped depression running spirally in each polishing padsurface continuously increases from an inner portion toward an outerportion. 5: The method recited in claim 1, wherein a distance W betweenturns of the at least one channel-shaped depression running spirally ineach polishing pad surface continuously decreases from an inner portiontoward an outer portion. 6: The method recited in claim 1, wherein eachpolishing pad surface has three spiral channel-shaped depressionsdisposed circularly around a midpoint of the respective polishing pad, adistance W between turns of the three spiral channel-shaped depressionscontinuously increasing from an inner portion to an outer portion, eachof the three spiral channel-shaped depressions merging into a circularform enclosing the three spirals in an edge region of the respectivepolishing pad without there being a connection between the circularchannels, and wherein an outer edge region is formed by a ring-shapedarea in an outer third of the respective polishing pad surface. 7: Themethod recited in claim 1, wherein a width of each of the at least onechannel-shaped depression running spirally in each polishing pad surfacecontinuously increases from an inner portion toward an outer portion. 8:The method as recited in claim 1, wherein a depth of each of at leastone channel-shaped depression running spirally in each polishing padsurface continuously increases from an inner portion toward an outerportion. 9: The method as recited in claim 1, wherein each suitablydimensioned circular cutout in the carrier plate is surrounded by threesegmented cutouts, each having an identical size and being separatedfrom one another by webs, with a distance among one another of in eachcase at most 110°, in a ring-shaped manner at a distance A from thecircular cutout. 10: The method as recited in claim 1, wherein eachsemiconductor wafer rotates in the respective suitably dimensionedcutout. 11: The method as recited in claim 1, wherein a rotation of eachsemiconductor wafer within the respective suitably dimensioned cutout inthe carrier plate is prevented by the semiconductor wafer being fixed inthe cutout. 12: The method as recited in claim 1, wherein the polishingagent is supplied on the front side and the rear side of thesemiconductor wafer in a pressurized manner through openings presentboth in the upper and in the lower polishing plate and also in the upperand in the lower polishing pad, and wherein nozzles for the polishingagent supply are integrated in the openings in the polishing plate. 13:The method as recited in claim 12, wherein an orientation of openings ofthe nozzles integrated in the polishing plate for the polishing agentsupply or openings in the polishing pad, relative to the polishing padsurface, lie in an angular range of from 45° to 90°. 14: The method asrecited in claim 13, wherein a quantity of the polishing agent emergingfrom the openings into the working gap per unit time in an innercircular region of the polishing pad is higher than a quantity thatemerges in the same time from the openings situated in an outerring-shaped region. 15: The method as recited in claim 1, wherein afront side of the at least one wafer is polished at the upper polishingpad.